Non-Patent Document 1 describes a conventionally known example of the structure of a non-volatile memory element. This element has a control gate formed on the side of a memory gate. Hereinafter, a process for manufacturing this element is described in order of steps with reference to drawings.
First, a structure shown in FIGS. 27A, 27B is formed. FIG. 27A is a plan and FIG. 27B is a sectional view taken along a line A–A′ in FIG. 27A. In other words, after a memory gate film 202 is formed on a silicon substrate 200, polycrystalline silicon 204 and an HTO (high temperature CVD silicon oxide) film 206 are formed thereon. Then, after a mask is formed in a prescribed area on the HTO film 206 using a lithography process, the polycrystalline 204 and the HTO film 206 are subjected to patterning by dry etching, and an electrode structure shown is formed. Next, as shown in FIG. 28 (FIG. 28A is a plan and FIG. 28B is a sectional view taken along a line A–A′ in FIG. 28A), the sides of the electrode structure are enclosed with an HTO film 208, and a memory gate 216 is produced. Then, after a polycrystalline silicon film is formed on the whole surface of the substrate covering the memory gate 216 and a mask is formed on the memory gate 216 using a lithography process, a control gate 212 is produced by selectively dry-etching the polycrystalline silicon as shown in FIG. 29. FIG. 29A is a plan and FIG. 29B is a sectional view taken along a line A–A′ in FIGS. 29A, 27B. Further, impurity diffusion regions 214 are formed by ion implanting. An interlayer-insulating film 217 is formed, so are contact plugs 218 on top of the impurity diffusion regions 214, the memory gate 216, and the control gate 212, and a structure shown in FIG. 30 is achieved. FIG. 30A is a plan and FIG. 30B is a sectional view taken along a line A–A′ in FIG. 30A.
Patent Document 1 describes a different process for manufacturing memory element from the one described above. In the process described in this document, after a control gate is formed, a memory gate is formed on the side of the control gate by etching back, enabling a memory element to be produced in one lithography process.
[Non-Patent Document 1]
Extended Abstracts of the International Conferences on Solid State Devices and Materials, Tokyo, 2003, pp204–205.
[Patent Document 2]
Japanese Patent Kokai Publication No. P2001-57394A